SI100B EE Part Project

MAC Systolic Array

Background

Systolic Array and Google TPU

From 2016 to 2021, Google released four generations of its own AI acceleration chip, the TPU (Tensor Processing Unit).

The TPU provides hardware-level arithmetic support for AI-specific application scenarios. The most important hardware part of the TPU is its 'Matrix Multiply Unit', which uses its special Systolic Array to improve the speed and power consumption of matrix operations such as convolution and matrix multiplication in AI tasks.

Introduction

Introduction

A Systolic Array is a homogeneous network of tightly coupled data processing units (DPUs), called cells or nodes.

Each node independently computes a partial result as a function of the data received from its upstream neighbours, stores the result within itself and passes it downstream.

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Introduction

Why Systolic Array?

  1. Simple and regular design
  2. Concurrency and communication
  3. Balancing computation with I/O

Tasks & Grading Policy

Tasks & Grading Policy

Main Task

Build an Multiply-Accumulated(MAC) Systolic Array in Logisim!

  • Week 1 & 2:

    1. Design before implementation: 10%
    2. Build Processing Element(PE): 10%
    3. Link the PE, build the main part of Systolic Array: 20%

  • Week 3 & 4:

    1. Control Signal: 10%
    2. Deal with Input Buffer: 20%
    3. Deal with Output Buffer: 20%
    4. Write an Report about the Project and your design: 10%
Good Luck & Have Fun!